The present invention generally relates to integrated circuits and particularly, but without limitation, to the design and fabrication of self-aligned local interconnects for interconnecting semiconductor devices in an integrated circuit.
As semiconductor technology continues to advance, a continuing trend is towards ultra large-scale integration with the fabrication of smaller and smaller integrated circuits containing more and more devices on a single semiconductor chip.
Scaling of devices has long been used to increase the density of logic and memory functions. This scaling has been possible because of improvements in photolithography and other process steps. However, as optical lithography reaches the end of the cost effective improvement curve, other approaches to improve density are needed.
Interconnect provides connections between NMOS and PMOS transistors and other components such as resistors and capacitors in a semiconductor chip. Interconnects are generally fabricated by first depositing and planarizing dielectric layers on the semiconductor devices and passive components. Next, feed-thrus are formed in the dielectric layers. Finally, conductors are formed and routed over the dielectric layers to connect the feed-thrus. A stack is formed of multiple layers of dielectrics, feed-thrus, and conductors to complete the circuit node interconnection. This process of fabricating interconnects is generally termed “metallization.” As the density of devices on the semiconductor chip is increased, the complexity of metallization has also increased.
Local interconnects can be a special form of interconnects. Local interconnects are generally used for short distances, such as within a functional cell. Conventional circuits use the same interconnect levels for both local and global connections.
Traditionally, diffusion regions to Vdd and Vss contacts require fabricating L shaped or T shaped bent diffusion regions extending towards Vdd and Vss lines from PMOS and NMOS diffusion regions, respectively. The bent regions are not preferred because they require more costly photolithography equipment to fabricate. Alternatively, Vdd and Vss rails may be extended over rectangular diffusion regions and contacts may be formed to the diffusion regions. However, it is inefficient to have the power rails over the diffusion regions because they occupy tracks that could be used for signals and they are no longer located at a cell boundary so they can not be shared between vertically adjacent cells.
It is within this context that embodiments of the invention arise.